A known non-volatile semiconductor memory device which is electrically rewritable and can be highly integrated is a NAND flash memory. The NAND flash memory includes a NAND string in which a plurality of memory cells are connected in series and the adjacent memory cells share a source/drain diffusion layer. The NAND string has ends connected to a bit-line and a source-line, respectively, via a select gate transistor. Such a NAND string configuration allows for a smaller unit cell area and a larger capacity than a NOR flash memory.
The memory cell in the NAND flash memory includes a semiconductor substrate and a tunnel insulating film, a charge accumulation layer (floating gate), an inter-gate dielectric film, and a control gate, which are stacked in this order on the substrate. The memory cell stores data in a non-volatile manner according to the charge accumulation state of the floating gate. The memory cell stores binary data using, for example, data “0” representing the high threshold voltage state in which the floating gate is injected with electrons and data “1” representing the low threshold voltage state in which electrons in the floating gate are discharged. The threshold voltage distribution for writing may be further divided to provide a multi-level storage such as a four-level or eight-level storage.
The NAND flash memory may be written with data usually by supplying the control gate of the memory cell with program voltages necessary for the charge accumulation. The program voltages are provided in a repeated and stepped-up manner to gradually change the threshold voltage of the memory cell to the desired threshold voltage. In this case, a large step width of the program voltage may allow for a rapid data write process, while increasing the threshold voltage distribution and thus reducing the reliability. Conversely, a small step width of the program voltage may decrease the threshold voltage distribution and thus improve the reliability, while slowing the data write process. It is thus necessary to set an appropriate step width according to the program speed of the memory. The same holds true for a charge-trap type non-volatile memory in which the charge accumulation layer includes an insulating film such as an MONOS film.